Method for forming bump of semiconductor device

ABSTRACT

A method for forming a bump of a semiconductor device including an adhesive applying step of applying an adhesive to a pad electrode of a semiconductor device, a solder grain attaching step of attaching one or more solder grains to the portion of the pad electrode where the adhesive is applied, and a solder melting step of forming a bump by melting the solder grains. In the solder melting step, a metallic core is put in the bump. Therefore, a semiconductor device where a highly reliable bump is formed is obtained through simple steps.

BACKGROUND OF INVENTION

1. Technological Field

This invention relates to a method for forming a bump on pad electrodesof a flip-chip type semiconductor device.

2. Background Technology

On semiconductor devices that are bonded by means of the flip-chipmethod, solder bumps are formed on the pad electrodes. Conventionalmethods to form such solder bumps include metal evaporation,electrolytic plating, and/or stud-bumping. However, each of the first orthird method has its own disadvantages: metal evaporation is inferior inprecision in terms of recent larger wafer sizes, finer bump pitches andmore complicated and dense bump shapes; and stud-bumping is expensivefor mass-production so it is only used for experimental products.Therefore, electrolytic plating is becoming the major method for bumpformation aimed at volume production.

FIG. 17 shows a conventional bump formed by electrolytic plating.

In the figure, 1 is a wafer; 2 a pad electrode made of aluminum; 3 apassivation film; 100 an electrolytic plating bump; 101 an undercoatmetallic film; 102 a copper core; and 103 a solder bump.

In order to form this bump, the undercoat metallic film 101 is formed byevaporating aluminum, chrome, and copper onto the wafer 1 using a vacuummetal evaporation method, in order to ascertain the reliability of thepad electrode of the semiconductor device and the electrolyticconnectivity. Then, plating resist is applied, and an appropriate partof the plating resist is opened to expose the undercoat metallic film101 on the pad electrode 2. Copper is electrolytically plated using theundercoat metallic film 101 as the common electrode to form the coppercore 102. Solder is also electrolytically plated. Next, the platingresist is removed, leaving the undercoat metallic film 101 in the bumpportion, and the other portion of the undercoat metallic film is etched.Finally, after applying a flux, the solder is melted in a reflow furnaceunder a nitrogen atmosphere to complete the plating bump 100.

However, this method for forming solder bumps also has problems asfollows.

First, it incurs high cost and is inflexible. Since equipment used insteps for forming photoresist and/or undercoat metallic film isexpensive and the wafer sizes that can be handled are limited, it takestime for switching when the wafer size is changed, or sizes out ofspecification can not be handled. Thus, this method leads to high costs,and it is impossible to form bumps on chips rather than on wafers.

The second problem is reliability. When solder bumps are bonded to thesubstrate, it is necessary to plate a copper core, which isapproximately 20 μm in thickness, in order to prevent solder bumps frombeing crushed and causing a short with the side of the semiconductordevice. Copper is a hard material and adheres strongly to the undercoatmetallic film. Hence, as chip sizes become larger, there are reliabilityproblems such as discontinuity caused by peeling of the surface, crackedsilicon, and so on, which are caused by stress under the copper core dueto the different coefficients of linear expansion of copper and siliconsubstrate when thermal variations occur due to heating or cooling.

Third, etching of the undercoat metallic film is a difficult step. Whenaluminum, chrome, or copper is used as the undercoat metal, for example,it has been difficult to etch the undercoat metallic film withoutetching lead and tin. Also, it is difficult to control the amount andtime of etching.

Meanwhile, a technique, in which solder is applied to leads ofelectronic parts or exposed patterns on a printed circuit board, hasbeen suggested (see Japanese Patent Application Laid-OpenNo.074459/1995).

A similar technology, applying this technique, has not be developed toform bumps on pad electrodes on semiconductor devices. Furthermore, noinformation has been disclosed regarding a method to prevent bumps frombeing crushed while the bumps are bonded onto the substrate when forminga bump by means of this technique.

The objective of this invention is therefore to provide a method to formbumps on semiconductor devices in order to manufacture reliable productswith simple steps, considering the above issues and situations.

DISCLOSURE OF INVENTION

In order to attain the above-mentioned objective, the present inventionincludes: a plating step to perform non-electrolytic plating on padelectrodes of semiconductor devices; an adhesive applying step to applyadhesive to non-electrolytic plated portions; a solder grain attachingstep in which one or more solder grains is caused to adhere to theportion where adhesive has been applied; and a solder melting step inwhich solder grains are melted to form bumps.

In the step in which solder grains are melted to form bumps, metalliccores are placed within the bumps. At least one metallic core for eachsolder bump is used for a part of or all of the solder grains so thatmetallic cores are present in bumps during the solder melting step.

Also, this invention can be applied in a manner such that theabove-mentioned metallic cores are mixed with solder grains and causedto adhere to portions where adhesive has been applied. Moreover, theabove-mentioned metallic cores can be placed in bumps during the soldermelting step by applying the metallic cores to the electrode portion inthe steps for adhesive application and metallic core attachmentindependent of the solder grain attaching step.

In addition, the adhesive application, solder grain attachment, andsolder melting steps in this invention consist of a high temperaturesolder adhesive applying step, high temperature solder grain attachment,and high temperature solder melting steps as well as low temperaturesolder adhesive application, low temperature solder grain attachment,and low temperature solder melting steps.

In this case, it is desired to perform the three high temperature stepsfirst and then perform the three low temperature steps. This ensuresthat the high temperature solder functions as a metallic core.

In this way, the present invention provides highly reliablesemiconductor devices using simple steps without expensive equipment. Itcan also deal easily with changes in wafer sizes.

Furthermore, selective non-electrolytic plating on aluminum allowssimplification of the manufacturing process and reduction of costs sinceformation of a common electrode on a wafer, which is used inelectrolytic plating, is not necessary.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIG. 1 shows a step flow diagram of a 1st embodiment of the method forforming a bump of a semiconductor device in the present invention.

FIG. 2 (a) to FIG. 2(f) show cross sections of the electrodes in themajor steps in the 1st embodiment.

FIG. 3 shows a cross section of a bump formed in the 2nd embodiment ofthe method for forming a bump of a semiconductor device in the presentinvention.

FIG. 4 (a) and FIG. 4(b) show cross sections of the electrode in themajor steps in a 3rd embodiment of the method for forming a bump of asemiconductor device in the present invention.

FIG. 5 shows a cross section of the state, where the semiconductordevice is bonded on the circuit board with the bump formed by means ofthe 2nd embodiment.

FIG. 6 shows a cross section of the state where three metallic cores areplaced within the solder bump by means of the 3rd embodiment.

FIG. 7 shows a step flow diagram of a 4th embodiment of the method forforming a bump of a semiconductor device in the present invention.

FIG. 8 (a) to FIG. 8(d) show cross sections of the electrodes in themajor steps at the first stage of the 4th embodiment.

FIG. 9 (a) to FIG. 9(c) similarly show cross sections of the electrodesin the major steps at the second stage of the 4th embodiment.

FIG. 10 is a step flow diagram of another embodiment employing metalliccore of the method for forming a bump of a semiconductor device in thepresent invention.

FIG. 11 shows a step flow diagram of a 5th embodiment of the method forforming a bump of a semiconductor device in the present invention.

FIG. 12 (a) to FIG. 12(e) show cross sections of electrodes in the majorsteps in the 5th embodiment as well.

FIG. 13 is a plan diagram of a semiconductor device on which metalliccores are placed within at least three solder bumps by means of the bumpformation on semiconductor devices in the present invention.

FIG. 14 is a plan diagram that shows the usage condition ofsemiconductor devices produced with the embodiments of bump formationson semiconductor devices in the present invention.

FIG. 15 is a cross sectional diagram that describes the state of sortingsemiconductor devices produced with the embodiments of bump formationson semiconductor devices in the present invention onto a tray.

FIG. 16 is a cross sectional diagram that describes the state of sortingsemiconductor devices produced with the embodiments of bump formationson semiconductor devices in the present invention onto a tray.

FIG. 17 shows the cross section of a conventional solder bump.

THE BEST FORMS TO IMPLEMENT THE INVENTION

The present invention will now be described with reference to theattached figures and diagrams.

1st Embodiment

First, the 1st embodiment of the present invention is described usingFIG. 1 and FIGS. 2(a)-2(f).

FIG. 1 shows a step flow chart, and FIG. 2 (a) to FIG. 2(f) show crosssections of the electrode portions in the major steps.

In a pre-treatment step S1, in FIG. 1, an oxide film on an aluminum padelectrode of a finished semiconductor device on the wafer 1 is removedas shown in FIG. 2(a).

Then, an activation step S2 is performed to non-electrolytically platenickel selectively on a pad electrode 2. Further, in a non-electrolyticnickel plating step S3, a nickel film 11 is non-electrolytically platedon the pad electrode 2 as shown in FIG. 2(b). 3 is a passivation film.

Next, in an adhesive applying step S4, the wafer 1 is soaked in achemical vat and then dried in order to selectively apply an adhesive 4to the exposed metallic portion, as shown in FIG. 2(c).

In a solder grain attaching step S5, solder grains 12 are then sprinkledonto the wafer 1 as shown in FIG. 2(d). In this implementation, thediameter of the solder grains is approximately 100 μm.

Further, in a post-treatment step S6, solder grains 12, which arepresent on the portions to which the adhesive 4 is not applied, areremoved by moderately brushing after a heat step to tentatively attach asolder grain to the electrode portion, as shown in FIG. 2(e). This stepleaves the solder grain 12 only on the portion to which the adhesive isapplied.

In this way, after solidifying the solder grain 12 on the metallicportion of the wafer 1, a flux is applied to the surface of the wafer 1as a flux application step S7. Then, by processing the wafer through areflow furnace as a solder reflow step S8, molten solder 14 becomesspherical due to the surface tension as shown in FIG. 2(f). Finally, thewafer is inspected in an inspection step S9 after rinsing and drying tocomplete solder bumps 10 on the wafer.

If the thickness of the solder film is not sufficient after the solderreflow step S8, it is necessary to repeat the adhesive application S4and other steps thereafter.

In the present embodiment, the diameter of the solder grain isapproximately 100 μm, and one solder grain adheres to one electrode.However, it is possible for multiple solder grains with a diameter of 50μm or less to adhere to one electrode.

2nd Embodiment

A 2nd embodiment of the present invention is described hereafter.

FIG. 3 shows a cross section of a solder bump formed with the 2ndembodiment. The 2nd embodiment of the present invention is the same asthe step in FIG. 1 except the activation step S2 and thenon-electrolytic nickel plating step S3 have been omitted.

In other words, it requires the pre-treatment step S1, then the adhesiveapplying step S4 to form an adhesive layer on the pad electrode 2, thesolder grain attaching step S5, the post-treatment step S6, the fluxapplication step S7 and the solder reflow step S8 to form the solderbump 10.

This embodiment is applicable to cases in which there are tolerances fordiffusion of tin or lead toward the pad electrode metal such as aluminumor for chemical compounds between metals.

The 1st implementation method, which includes the above-mentionedactivation S2 and the non-electrolytic nickel plating step S3, and the2nd implementation method are selectively applicable for each embodimentdescribed hereafter. Therefore, even though a part of the 1st or 2ndembodiment is to be employed, each of the implementations mentionedhereafter is not to be limited to either implementation method.

In addition, non-electrolytic plating is not to be limited to nickel; itis also applicable to gold, silver or chrome plating, for example.Moreover, there can be multiple layers or composite plating of suchmaterials.

3rd Embodiment

Next, a 3rd embodiment of the present invention is described.

FIGS. 4(a) and 4(b) demonstrates cross sections of the electrodeportions in major steps.

This 3rd implementation method is also based on the process shown inFIG. 1 to form bumps. However, a spherical metallic core 13, which ismade of copper for example, is placed into a solder grain 12 in thisembodiment as shown in FIGS. 4(a) and 4(b).

In this embodiment, the diameter of the metallic core 13 isapproximately 20 μm, where the diameter of the solder grain 12 is 100μm.

In this way, making the diameter of the metallic core 13 smaller thanthe film thickness of the solder grain 12 (the thickness isapproximately 30 μm) allows ascertaining the solder quantity relative tothe metallic core 13 sufficiently. This eliminates the need to replenishthe solder.

In the process sequence, a solder bump is formed as shown in FIG. 4 (b)in the following sequence: the solder grain 12 containing the metalliccore 13 is secured to the metallic portion of the wafer 1 with theadhesive 14; flux is then applied to the surface of the wafer 1 in theflux application step S7; the wafer is processed through a reflowfurnace in the solder reflow step S8, whereby a ball 14 of molten soldercontaining the metallic core 13 is produced, the ball is maintainedspherical by surface tension. The solder bump 10 is formed in thismanner.

Even though solder grains that contain metallic cores 13 are used, ifthe solder film thickness is insufficient after the solder reflow stepS8, the adhesive applying step S4 and subsequent steps should berepeated. However, it is not necessary to use solder grains 12 thatcontain metallic core, and the diameter of the solder grains can bedetermined according to the required solder film thickness.

FIG. 5 shows an example in which a semiconductor device 1a, with asolder bump formed with the 3rd implementation method, is bonded to agold-plated connection electrode 202 of a circuit substrate 200. Themetallic core 13 here functions as a spacer between the semiconductordevice 1a and the substrate 200. In addition, since the metallic core 13is wrapped with solder 14a and does not directly contact the nickel film11, stress is eased, resulting in a highly reliable connection with easybonding.

It is also possible to put multiple metallic cores 13 inside a soldergrain 12 to obtain a solder bump 14 such as shown in FIG. 6.

4th Embodiment

Next, a 4th embodiment of the present invention is described.

FIGS. 7, 8 and 9 demonstrate the 4th embodiment of the presentinvention; FIG. 7 is the step flow diagram of this embodiment; FIG. 8(a) to FIG. 8(d) are cross sections of electrodes during the major stepsat the first stage; and FIG. 9 (a) to FIG. 9(c) are cross sections ofelectrodes during the major steps at the second stage.

This embodiment method includes: steps at the first stage from S1 to S8,in which solder grains and metallic cores are mixed and caused to adhereto effect the solder-reflow, and steps at the second stage from S9 toS14, in which only solder grains adhere to the adhesive to complete thesolder-reflow.

At the first stage, as shown in FIG. 8(a), the adhesive applying step S4is performed, then the solder grain 12 and the metallic core 13 aremixed and attached to the adhesive 4 in the grain attaching step S5 asshown in FIG. 8(b). In this case, the ratio of the solder grains 12 tothe metallic cores 13 depends on the number of bumps per chip unit andshould be such that the chip is almost parallel when it is bonded. Then,as shown in FIG. 8(c), after the solder grains 12 and the metallic cores13 not on pad electrode portions are removed, and the handling step S6is performed. Next, the flux application step S7 and then the solderreflow step S8 are performed.

Each step at the second stage of this implementation method is performedwhen the solder film 14 thickness is insufficient relative to themetallic core 13. As shown in FIG. 9(a), the adhesive is applied againto the solder bump that has been formed in the first stage steps in theadhesive applying step S9. Then, the solder grain attaching step S10 andthe post-treatment step S11 are performed accordingly so that the soldergrains 12 adhere to the pad electrode portion only as shown in FIG.9(b). Moreover, the flux application step S12 and the solder reflow stepS13 are performed to form the solder bump 10 as shown in FIG. 9(c).

Also in this 4th implementation method, the second stage steps arerepeated if the amount of solder is insufficient after only one cycle ofthe second stage steps. Conversely, if the solder bumps 10 are completedafter the first stage steps from S1 to S8, each step from S9 to S13 atthe second stage can be omitted.

There are various methods for putting the metallic cores 13 into solderbumps 10: a method in which the metallic core 13 is placed in the soldergrains 12 in advance; a method in which the solder grains 12 and themetallic core 13 are mixed; a method in which both the above methods areperformed together; a method in which the solder grains with and withoutthe metallic core 13 inserted are mixed before being supplied; and amethod in which the metallic core 13 and the solder grains 12 aresupplied separately.

FIG. 10 is the step diagram of the method in which the metallic core 13and the solder grains 12 are supplied separately. The step S5 in whichthe solder grains and the metallic core are caused to adhere is changedto the step in which metallic core only is attached. Accordingly, theflux application step S7 and the solder reflow step S8 are omitted.

5th Embodiment

Next, a 5th embodiment of the present invention is described.

FIG. 11 is the step diagram of this implementation method, and FIGS.12(a)-12(c) show the cross sections of the electrode portions during themajor steps.

In this implementation method, high temperature molten solder forms theinside layer of the solder bumps, and subsequently low temperaturemolten solder forms the outside layer of the solder bumps.

As previously described in FIG. 1 and FIG. 7, the pre-treatment stepS11, the activation step S12, and the non-electrolytic nickel platingstep S13 are performed, followed by the adhesive applying step S14, inwhich the adhesive 4 is applied.

Subsequently, the high temperature solder grain attaching step S15 andthe post-treatment step S16 are performed. Then, as shown in FIG. 12(b),the high temperature solder grain 12a adhere only to the portion of theadhesive 4.

Moreover, after the flux application step S17, the solder reflow stepS18 is performed to form the inside layer 14a of the solder bump asshown in FIG. 12 (c).

Later, in another adhesive applying step S19, the adhesive 4 is appliedto the outside of the bump inner layer 14a made of high temperaturemolten solder. Further, the low temperature solder grain attaching stepS20 and the post-treatment step S21 are performed. As a result, as shownin FIG. 12 (d), the low temperature molten solder 12b adheres only tothe outside of the bump inner layer 14a.

Finally, after the flux application step S22, the outer layer portion14b of the solder bump is molten-formed, with the solder reflow stepS23, to complete the entire solder bump 14.

Using the solder bumps formed with this 5th implementation method, theinner layer 14a functions as a metallic core when the semiconductordevice is mounted on a circuit board. This is because only the outerlayer portion 14b, which is made of low temperature molten solder, ismelted to perform the mounting.

Regarding the solder grain material, Pb/Sn=95/5, for example, is usedfor the high temperature molten material; Pb/Sn=40/60, for example, isused for the low temperature molten material. The ratio of Pb/Sn is notlimited to the above. Also, not only Pb/Sn but also Ag/Sn/Zn, Zn/Sn,Sn/Cu, Sn/Ag/Bi, Sn/In, and the like, can be applied as solder material.

6th Embodiment

Next, a 6th embodiment of the present invention is explained.

In this implementation method, when the semiconductor device has threeor more pad electrodes, solder bumps which have metallic cores 13 set onat least three pad electrodes or which have the inner layer 14a made ofhigh temperature molten solder are to be formed.

For example, in case of a semiconductor device 20 with a large number ofsolder bumps 14, as shown in FIG. 13, it is possible to maintain thesemiconductor device and circuit board parallel to one another byputting metallic cores in at least three of these solder bumps 14.

It is most desired that the metallic cores 13 be placed in the foursolder bumps at each corner of the semiconductor device. In such a case,after the adhesive applying steps, S4 and S14, metallic cores, soldergrains with metallic cores, or high temperature molten solder grains areattached to the four corner electrode pad portions, then each step thathas previously been mentioned is performed.

Each implementation method mentioned above is applicable tosemiconductor devices either as wafers or as chips.

Also, if a semiconductor device 20 that has bumps formed with anyimplementation method stated above is retained on a palette 30 with anadhesive 21, as shown in FIG. 14, the semiconductor device is oftenremoved from the palette 30 and sorted onto a tray during mounting.

In such a case, it is possible to automate carrying and sorting from thepalette 30 to trays (no figure) by using a material, for which theadhesion is lowered by light or heat for adhesive 21. (For example,STRIP MASK #448T made by Asahi Chemical Laboratory is an adhesive forwhich the adhesion is lowered with heat.)

Specifically, if the adhesive 21 has a characteristic so that theadhesion is lowered with light, as shown in FIG. 15, the palette 30 ismade of transparent material, and light is applied from beneath thetrays. If the adhesive 21 has a characteristic so that the adhesion islowered with heat, as shown in FIG. 16, the palette 30 is heated byproviding a heater 40 under the palette 30.

In this way, after the strength of the adhesive is lowered, it becomespossible to remove semiconductor devices from the palette 30 with avacuum chuck 50, as shown in FIG. 16.

Moreover, when semiconductor devices such as chips are mounted oncircuit boards, extra bumps that are irrelevant for electricconnectivity can be formed by means of each implementation methodpreviously stated. This makes such extra bumps function as spacers,making it possible to mount the semiconductor devices parallel to thecircuit boards.

In this case, if a resist film is formed on the circuit board portionscorresponding to the extra bumps, the extra bumps are not widened butfunction without failure as spacers while the semiconductor devices aremounted.

The present invention is not limited to the above-mentionedimplementation methods but is applicable by altering any implementationmethod within the scope of the concept.

INDUSTRIAL APPLICABILITY

The present invention relating to the method for forming a bump of asemiconductor device is applicable to TAB type semiconductor device aswell as flip-chip type.

What is claimed is:
 1. A method for forming a bump of a semiconductordevice comprising:a plating step of applying non-electrolytic plating ona pad electrode of a semiconductor device, an adhesive applying step ofselectively applying an adhesive onto the pad electrode of thesemiconductor device by soaking a non-electrolytic plating portionformed in the plating step into a chemical material and drying thechemical material, a solder grain attaching step of adhering at leastone solder grain to the portion where the adhesive is applied, and asolder melting step of melting the solder grain to form the bump.
 2. Themethod for forming a bump of a semiconductor device as claimed in claim1, wherein a metallic core is placed in the bump in the step where theabove-mentioned solder grain is melted to form the bump.
 3. The methodfor forming a bump of a semiconductor device as claimed in claim 2,wherein at least one metallic core part of or in all is placed in a partof or in all the solder grain in advance so that the metallic coreexists in the bump during the solder melting step.
 4. The method forforming a bump of a semiconductor device as claimed in claim 2, whereinthe metallic core is mixed with the solder grain and caused to adhere tothe portion where the adhesive is applied so that the metallic coreexists in the bump during the solder melting step.
 5. The method forforming a bump of a semiconductor device as claimed in claim 2, whereinthe metallic core is caused to adhere to an electrode portion in anadhesive applying step and a metallic core attaching step which areseparate and independent of the solder grain attaching step so that themetallic core exists in the bump during the solder melting step.
 6. Themethod for forming a bump of a semiconductor device of claim 1, whereinthe adhesive applying step, the attachment step for the solder grain,and the solder melting step are employed at least once.
 7. The methodfor forming a bump of a semiconductor device as claimed in claim 3,wherein the diameter of the metallic core placed in the solder grain issmaller than a film thickness of the solder grains.
 8. The method forforming a bump of a semiconductor device as claimed in claim 1, whereinthe adhesive application, solder grain attachment, and solder meltingsteps comprise first temperature solder adhesive application, firsttemperature solder grain attachment, and first temperature soldermelting steps as well as second temperature solder adhesive application,second temperature solder grain attachment, and second temperaturesolder melting steps, second temperature being lower than firsttemperature.
 9. The method for forming a bump of a semiconductor deviceas claimed in claim 8, wherein the first temperature solder adhesiveapplication, first temperature solder grain attachment, and firsttemperature solder melting steps are performed, and then the secondtemperature solder adhesive application, second temperature solder grainattachment, and second temperature solder melting steps are performed,and the first temperature solder forms the metallic core.
 10. The methodfor forming a bump of a semiconductor device as claimed in claim 2,wherein when the semiconductor device has three or more pad electrodes,solder bumps in which the metallic cores are put on at least three padelectrodes are formed.
 11. The method for forming a bump of asemiconductor device as claimed in claim 10, wherein said at least threepad electrodes have been placed in specific locations in advance. 12.The method for forming a bump of a semiconductor device as claimed inclaim 11, wherein said at least three pad electrodes that have beenplaced in specific locations in advance are placed on four corners ofthe semiconductor device.
 13. The method for forming a bump of asemiconductor device, wherein the bums is formed on the semiconductordevice as a wafer by mean as claimed in claim
 1. 14. The method forforming a bump of a semiconductor device, wherein the bump is formed onthe semiconductor device as a chip by the method as claimed in claim 1.15. The method for forming a bump of a semiconductor device as claimedin claim 14, wherein the semiconductor device as the chip is retained ona palette by means of an adhesive.
 16. The method for forming a bump ofa semiconductor device as claimed in claim 15, wherein the semiconductordevice as the chip retained on the palette is removed from the paletteand placed on a tray.
 17. The method for forming a bump of asemiconductor device as claimed in claim 16, wherein the strength of theadhesive is lowered by heat when the semiconductor device as the chip isremoved from the palette.
 18. The method for forming a bump of asemiconductor device as claimed in claim 16, wherein the strength of theadhesive is lowered by light when the semiconductor device as the chipis removed from the palette.
 19. The method for forming a bump of asemiconductor device as claimed in claim 1, wherein saidnon-electrolytic plating is at least one layer selected from the groupconsisting of nickel, gold, copper, chromium and a combination thereof.20. The method for forming a bump of a semiconductor device as claimedin claim 1, wherein the pad electrode is formed of aluminum.